ADZS-21371-EZLITE【PDF 9/56 页】KIT EVAL EZLITE ADZS-21371

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ADSP-21371 / ADSP-21375

Serial ports operate in five modes:

? Standard DSP serial mode

? Multichannel (TDM) mode with support for packed I 2 S

mode

? I 2 S mode

? Packed I 2 S mode

? Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I 2 S protocols (I 2 S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I 2 S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I 2 S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I 2 S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional ? -law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The ADSP-21371 S/PDIF receiver/transmitter has no separate

DMA channels. It receives audio data in serial format and con-

verts it into a biphase encoded signal. The serial data input to

the receiver/transmitter can be formatted as left justified, I 2 S or

right justified with word widths of 16, 18, 20, or

24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources such as the

SPORTs, external pins, the precision clock generators (PCGs),

and are controlled by the SRU control registers.

The ADSP-21375 does not have an S/PDIF-compatible digital

receiver/transmitter.

Input Data Port (IDP)

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

but data is sent to the FIFO as 32-bit words (that is, one-half of a

frame at a time). The processor supports 24- and 32-bit I 2 S, 24-

and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi-

fied formats.

Precision Clock Generator (PCG)

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface (SPI) ports, one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a 2-wire interface

(TWI), and two general-purpose timers.

Serial Peripheral (Compatible) Interface

The ADSP-21371/ADSP-21375 SHARC processors contain two

serial peripheral interface ports (SPIs). The SPI is an industry-

standard synchronous serial link, enabling the SPI-compatible

ports of the processors to communicate with other SPI compati-

ble devices. The SPI consists of two data pins, one device select

pin, and one clock pin. It is a full-duplex synchronous serial

interface, supporting both master and slave modes. The SPI port

can operate in a multimaster environment by interfacing with

up to four other SPI-compatible devices, either acting as a mas-

ter or slave device.

The SPI-compatible peripheral implementation also features

programmable baud rates and clock phases and polarities. The

SPI-compatible port uses open drain drivers to support a multi-

master configuration and to avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface stan-

dard. The UART port also includes support for 5 to 8 data bits, 1

or 2 stop bits, and none, even, or odd parity. The UART port

supports two modes of operation:

? PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

? DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

into two 32-bit words. The serial protocol is designed to receive

audio channels in I 2 S, left-justified sample pair, or right-justified

mode. One frame sync cycle indicates one 64-bit left/right pair,

Rev. D | Page 9 of 56 | April 2013

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